ASIC Synthesis and Timing Engineer

VirtualVocations


Junior QA Engineer
VirtualVocations • Los Angeles, CA, United States • via Talent.com
14 hours ago
Full–time
Apply on Talent.com
Job highlights
Identified by Google from the original job post
Qualifications
Bachelor's degree in Computer Science, Software Engineering, Information Systems, or a related field
1-3 years of experience with applications testing and automation
Proficient in at least one programming language (Python, Java, C#, or C)
2 more items(s)
Responsibilities
Develop and execute performance test scripts using LoadRunner and JMeter
Monitor and analyze test results to identify issues and optimize application performance
Collaborate with cross-functional teams to ensure high-quality application code releases
Job description
A company is looking for a Junior QA Engineer.

Key Responsibilities

Develop and execute performance test scripts using LoadRunner and JMeter

Monitor and analyze test results to identify issues and optimize application performance

Collaborate with cross-functional teams to ensure high-quality application code releases

Required Qualifications

Bachelor's degree in Computer Science, Software Eng...
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K2 Space


ASIC Synthesis and Timing Engineer
K2 Space • Los Angeles, CA, United States • via ZipRecruiter
10 hours ago
$1.3L–$2L a year
Full–time
Apply directly on ZipRecruiter
Job highlights
Identified by Google from the original job post
Qualifications
B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field
2+ years of experience in ASIC design for high-performance blocks of SoCs
Proven end-to-end expertise in RTL-to-GDSII flows using industry tools (Synopsys, Cadence, or Siemens)
17 more items(s)
Benefits
Base salary range for this role is $130,000 – $200,000 + equity in the company
Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks
Responsibilities
We are looking for an ASIC Synthesis and Timing Engineer to work on implementation of complex SoCs for next-generation satellite and space systems
You will develop the timing constraints and validate them—from RTL handoff to synthesis —and collaborate closely with architecture, RTL design, DFT, and physical design team
You'll be a key contributor in achieving timing closure, optimizing PPA, and supporting design integration with external partners
13 more items(s)
Job description
K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by $450M from leading investors including Altimeter Capital, Redpoint Ventures, T. Rowe Price, Lightspeed Venture Partners, Alpine Space Ventures, and others – with an additional $500M in signed contracts across commercial and US government customers – we're mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space.

The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today's and tomorrow's massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits.

With multiple launches planned through 2026 and 2027, we're Building Bigger to develop the solar system and become a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a groundbreaking Series C space startup, we'd love for you to apply.

The Role

We are looking for an ASIC Synthesis and Timing Engineer to work on implementation of complex SoCs for next-generation satellite and space systems. You will develop the timing constraints and validate them—from RTL handoff to synthesis —and collaborate closely with architecture, RTL design, DFT, and physical design team. You'll be a key contributor in achieving timing closure, optimizing PPA, and supporting design integration with external partners. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. In your first 6 months, you will develop and implement new SoC sub-systems for satellite communications and beyond. In your first two years, you will have contributed to developing cutting-edge SoCs that will fly in space.

Responsibilities
• Work on the RTL-to-Synthesis flow: Do synthesis at block and top level, Work with physical design team to integrate the floorplan information for physical synthesis.
• Develop and maintain design methodologies, scripts, and automation to optimize performance, power, and area (PPA).
• Collaborate with front-end engineers to assure timing closure, and efficient design iteration.
• Drive timing closure across multiple voltage and process corners, including sign-off with foundry-qualified tools.
• Own Lint, CDC and UPF checks and drive collaboration to close out issues.
• Develop an end to end formal verification methodology without any gap to deliver on full confidence functionality between the RTL and the post layout netlist.
• Manage and technically guide external physical design partners and service vendors, ensuring alignment on milestones, deliverables, and quality standards.
• Work with EDA vendors to debug and optimize tool flows, and evaluate new methodologies.
• Support chip bring-up and debug through close collaboration with post-silicon and test teams.
• Support your product through production and spaceflight.