Verification Engineer PCI e USB Perl |4 8 yrs

Job Description : Minimum 3 to 4 years of experience in System Verilog HVL. Minimum 2 to 3 years of experience in UVM. Hands on experience of developing assertion, checkers, coverage and scenario creation. Must have executed at least 2 SoC Verification project Experience in developing test and coverage plan, Verification environment and validation plan. Knowledge of atleast one industry standard protocols like Ethernet, PCIe, MIPI, USB or similar is required. Expertise in IP as well as SOC verification Perl shell scripting is a good to have