Agasthya App Labs Design Verification Engineer System Verilog

Job Description : Minimum 4+ years of experience working of SV and UVM methodology. Expertise in Verification Environment development, Expertise in deriving Feature List, Test plan, Erroneous, Directed and Random Testsuit development and debugging. Expertise in deriving Functional coverage matrix, Assertion Matrix etc. Should be capable to achieve closure on Functional and Code coverage, and regression management Expertise in PCIe legacy and PCIe Gen3, Gen4, Gen5 protocols is must. Expertise in verifying any type of PHY controller will be advantageous. Expertise in IP as well as SOC verification Perl shell scripting is a good to have