General Verification Engineer System Verilog SoC RTL Design |4 8

Job Description : One of our IT MNC clients is scouting for General Verification Engineer: Minimum 2 years of team lead experience. Minimum 4 years of experience in development of SV based testbench. Minimum 4 years of experience in development of SV based testbench. Minimum 4 years of experience in verification of SoC or reasonably big size RTL design. Project Planning Development, Verification and Validation Plan and Project Schedule participation. Architecture definition testbench architecture supporting multi language, multi tools and multi methodologies. HDL Coding Verilog. HVL Coding System Verilog. Development : Testbench Coding, Test Scenario Coding Definition, Assertion, protocol checkers and functional coverage coding. Constrained Random Verification System Verilog. Standards: Should have exposure to Ethernet, PCI, MIPI, USB, HBM specifications. Configuration Management Review and Audit participation