ASIC Verification Engineer Senior Engineer System Verilog UVM |3

Job Description :1. Should have strong working experience on Power Aware and UPF based verification2. Low Power & UFP with System Verilog and UVM.3. Must have executed at least 2 SoC Verification projects4. Languages & Methodology: Verilog, VHDL, Perl, Shell Scripting, C C++, SystemC5. Protocols: I2C, SPI, AMBA AHB & APB, Ethernet, PCIe PHY Layer6. Simulators Tools: Incisive ES, SimVision, Questa sim, Visualizer 7. Experience in UVM System Verilog, VCS simulator, Verdi8. Experience with UVM based test bench, coverage closure. Scripting skills (Python, Perl)+. Experience with Ethernet (1G 10G 100G) and Networking Chips Verification.10. Experience with FPGA Design Verification is plus.11. For Senior Manager: Minimum 2 years of experience in handling a team of 5 to 10 engineers.