Senior RTL Design Engineer

As a SoC design engineer at Synopsys, you will be working on the cutting-edge of Semiconductor design, verification and implementation of digital IP blocks for our next generation of designs. You will be working in a team environment, and will be expected to contribute to the team's success by sharing your knowledge and expertise.

The ideal candidate will have a strong understanding of digital design principles, and will be able to work independently with minimal supervision.

Primary Duties:
• Design, develop, and verify digital integrated circuits (ICs) for use in SoCs
• Work with architects to understand system requirements and microarchitecture specifications
• Develop RTL code using Verilog or System Verilog
• Perform Lint, FPGA synthesis
• Run simulations to verify the functionality of the design, both SoC and IP level.
• Generate documentation for the design
• Interface with other teams working on related IP to ensure smooth integration of the IP into the SoC
• Assist in the development of verification plans and test benches
• Perform silicon bring-up and debug
• Stay up-to-date on industry trends and new technologies

Required skills and Qualifications:
• Bachelor's or Master's degree in Electronics, Electrical or Computer engineering.
• 5+ years' experience in SoC design and verification
• Understanding of Computer architecture and SoC architecture
• Working knowledge of C programming language
• Expertise in Verilog, System Verilog
• Strong understanding of digital logic design principles