Principal CXL / PCIe Microarchitect & Design Engineer ( Hyderabad )

Staff/Sr.Staff/Principal CXL/PCIe Microarchitect & Design Engineer

Hyderabad

Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad

A US based well-funded product-based startup looking for Highly talented ASIC / RTL / Logic Design Engineers for the following roles.

Candidate should have minimum 3 -12years of direct hands on RTL coding experience on CXL and PCIe IP or Controllers, with additional uArch/RTL background

Staff/Sr.Staff/Principal CXL/PCIe Microarchitect & Design Engineer

A well-funded US based hardware product startup is looking for talented CXL/PCIe Microarchitect and Design Engineer with deep expertise in high performance controller design and IP integration. This is a great opportunity to help design high performance compute and memory systems that push the boundaries on performance, energy efficiency and scalability. This is a full-time position based in Hyderabad, India.

Responsibilities
• Architectural exploration of CXL and PCIe IP for building power, performance and area efficient memory expansion cards and SoCs
• Microarchitecture development and documentation of high performance CXL/PCIe IP
• Perform efficient RTL coding in Verilog or System Verilog towards IP development, and integrate CXL/PCIe IP modules in building memory expansion cards and SoCs
• Work with systems & firmware teams to help bring up CXL and PCIe on silicon platforms
• Work with verification and performance teams to make sure design is functionally correct and meets performance targets
• Work with emulation and FPGA teams for design prototyping and functional/performance evaluation
• Take ownership of Arch, uArch, Design and Integration of CXL/PCIe IP and ensure design is of the highest quality

Requirements
• Prior hands-on work experience in high performance CXL and PCIe IP or controller design
• Deep experience as a Microarchitect and RTL design engineer in developing high performance digital IP
• Understanding of high performance and low power microarchitecture techniques and logic design principles
• Proficiency in Verilog or System Verilog coding, and ability to identify PPA efficiency enhancements in RTL
• Experience with front end ASIC design EDA tools like simulators, waveform debuggers, IDEs, etc
• Master’s, PhD or bachelor’s degree in relevant subject area

Contact:

Uday

Mulya Technologies

muday_bhaskar@yahoo.com

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