Senior Design Verification Engineer Network Protocols |6 8 yrs|
- Category: Software Developer Jobs
- Location: Ahmedabad, Gujarat
- Job Type: Full Time / Part Time
- Salary: Estimated: $ 17K to 22K
- Published on: 2025/09/20
Design Verification (Sr. Verification Engineer)Position Type : PermanentTotal Experience : 6 8 yearsJob Location : Ahmedabad (C.G.Road) Bangalore (WhiteField), Candidates for now will work from home until the Pandemic.Notice Period OPEN : Max upto +0 daysJOB REQUIREMENTS : Minimum 6 years experience in ASIC FPGA verification, including verification of complex ASICs atchip level Expertise in System Verilog and UVM Knowledge of C and or Python preferred Networking protocol (i.e. Ethernet, OTN) and or FEC experience is a must Basic knowledge of SerDes and ADC DAC a plus Expertise in independently building SV UVM test benches Expertise in developing test cases and test plans Functional coverage, code coverage closure experience a must Gate sims and debugging. Experience in lab validation and bring up activities is a plus
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